An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis. - 2015

PROJECT TITLE:

An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis. - 2015

ABSTRACT:

This project proposes an economical constant multiplier architecture primarily based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for coming up with a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically modification in real time. To design an efficient reconfigurable FIR filter, in keeping with the proposed VHBCSE algorithm, two-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the two-D house of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally inside each coefficient. This technique is capable of reducing the average likelihood of use or the switching activity of the multiplier block adders by 6.a pair ofpercent and 19.sixp.c as compared to that of 2 existing two-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the typical power consumption by thirty twop.c and 52percent together with an improvement in the area power product (APP) by 25p.c and 66percent compared to those of the 2-bit and three-bit BCSE algorithms respectively. As regards the implementation of FIR filter, enhancements of thirteen% and 28p.c in area delay product (ADP) and seventy six.one% and seventy seven.8percent in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the sooner multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient mounted purpose reconfigurable FIR filter synthesis.

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