A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT - 2015


We have a tendency to present an economical combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, that includes log2 N - 1 SDC stages, and one SDF stage. The SDC processing engine is proposed to achieve 100p.c hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, together with each adders and multipliers. Thus, the specified range of complex multipliers is reduced to log4 N - 0.five, compared with log2 N - one for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture needs roughly minimum number of complicated adders log2 N + 1 and complicated delay memory 2N + one.5log2 N - one.5.

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