PROJECT TITLE :

Novel Multilevel Inverter Design with Reduced Device Count

ABSTRACT:

A new multilayer inverter topology is proposed in this study. We propose a novel multilevel inverter architecture with a lower device count by combining two well-known topologies, such as the cascaded H-bridge multilevel inverter topology and the multi-string multilevel inverter topology. In order to reduce hardware size, as well as cost and complexity, the "Reduce device count" concept was developed. This topology allows us to get a level of output of 31 with only ten switching devices and four dc sources by using this topology. The suggested multilevel inverter system's approach and system design are detailed in depth, and simulation results are used to verify them.