Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding


In the last few years, the topic of approximation computing has garnered a lot of interest, especially in the context of Signal Processing. Accurate computation can be used to benefit from the human imperceptibility of computing in image and video compression algorithms such as JPEG, MPEG and so on, which makes them ideal candidates for approximate computation. Aside from the fact that the level of hardware approximation is fixed, present approximate designs are not adaptive to input data. For example, the output quality varies substantially for different input videos when an MPEG encoder is configured with a fixed approximate hardware configuration (i.e., a fixed level of approximation). With the goal of maintaining a specific Peak Signal-to-Noise Ratio (PSNR) threshold for any video in mind, this study proposes a reconfigurable approximation MPEG encoder architecture that optimises power usage. Thus, we construct reconfigurable adder/subtractor blocks with the ability to modify their approximation level (RABs), which we then incorporate these blocks in MPEG encoder motion estimation and discrete cosine transform modules. During runtime, we suggest two strategies for automatically modifying the approximation degree of the RABs in these two modules. According to the experimental results, we may achieve a power savings of up to 38% over a typical non-approximated MPEG encoder architecture by dynamically altering the degree of hardware approximation in accordance with the input video. Despite the fact that the proposed reconfigurable approximation architecture is provided for the specific scenario of an MPEG encoder, it can be simply applied to other DSP applications.

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