Enhanced Model and Real-Time Simulation Architecture for Modular Multilevel Converter - 2017


This paper presents i) identical model of the [*fr1]-bridge modular multilevel converter (HB-MMC) that is suitable for real-time applications, ii) a hybrid central-processing unit/field-programmable gate array (CPU/FPGA)-based mostly architecture for real-time simulation of electromagnetic transients of systems that include HB-MMC, and iii) a novel arrangement for sorting results referred to as the “sub-module (SM) rank list”, that tackles the bottleneck for parallel implementation of the MMC arm model solver on the FPGA. The Adam-Bashforth (AB) methodology is used for numerical integration of the HB-SM capacitor model. The second-order AB technique provides a relentless admittance matrix of the HB-MMC and, so, reduces computational burden while offering the identical accuracy as that of the widely used Trapezoidal technique. The CPU/FPGA-based architecture is optimized to obtain maximum parallelism of the HB-MMC model implementation, adopting a commonplace, single-precision, floating-purpose computational engine. The proposed sorting arrangement is independent of the used sorting algorithm and its application to the odd-even bubble sorting scheme is presented during this paper. The proposed architecture offers a simulation time-step of 825 ns whereas including the sorting module because the SM capacitor voltage-balancing management unit. This enables accurate analysis of MMC controls based on either software-in-the-loop or hardware-in-the-loop approaches. Performance and accuracy of the MMC model and the hybrid CPU/FPGA-based mostly design are evaluated based mostly on a group of case studies on a 401-level HB-MMC-based mostly HVDC station and verified based mostly on offline simulation ends up in the PSCAD/EMTDC surroundings.

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