PROJECT TITLE:

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures - 2015

ABSTRACT:

This project presents many techniques utilized to resolve issues surfacing when applying scan bandwidth management to massive industrial multicore system-on-chip (SoC) styles with embedded check knowledge compression. These designs cause important challenges to the channel management theme, flow, and tools. This project introduces several check logic architectures that facilitate preemptive take a look at scheduling for SoC circuits with embedded deterministic test-based mostly check data compression. The same solutions enable economical handling of physical constraints in realistic applications. Finally, state-of-the-art SoC check scheduling algorithms are rearchitected accordingly by creating provisions for: 1) putting in time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based mostly on scan knowledge volume; and four) a lot of flexible core-wise usage of automatic check equipment channel resources. A detailed case study is illustrated herein with a variety of experiments permitting one to find out a way to tradeoff different architectures and test-related factors.