PROJECT TITLE:

Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing - 2015

ABSTRACT:

Fault tolerant techniques will extend the ability savings achievable by dynamic voltage scaling by trading accuracy and/or timing performance against power. Such energy enhancements have a sturdy dependency on the delay distribution of the circuit and also the statistical characteristics of the input signal. Independently, programmable truncated multipliers also achieve power advantages at the expense of degradation of the output signal-to-noise ratio. In this brief, a mix of programmable truncated multiplication is used among a fault tolerant digital signal processing (DSP) structure in that the supply voltage is reduced beyond the critical timing level. Timing modulation properties of truncated multiplication are analyzed and demonstrated to improve the performance of fault tolerant designs, reducing error correction burdens, and increasing the system operating voltage range. Combining both power strategies leads to lower energy consumption levels, that improve the energy savings beyond that expected when applying a mixture of both techniques with the original DSP.