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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. Low-Power Programmable PRPG With Test Compression Capabilities - 2015
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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Low-Power Programmable PRPG With Test Compression Capabilities - 2015

PROJECT TITLE:

Low-Power Programmable PRPG With Test Compression Capabilities - 2015

ABSTRACT:

This project describes an occasional-power (LP) programmable generator capable of manufacturing pseudorandom take a look at patterns with desired toggling levels and enhanced fault coverage gradient compared with the most effective-to-date engineered-in self-test (BIST)-based mostly pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a hoop generator) driving an applicable phase shifter, and it comes with a variety of options permitting this device to provide binary sequences with preselected toggling (PRESTO) activity. We tend to introduce a technique to automatically select many controls of the generator providing straightforward and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this project proposes an LP check compression methodology that permits shaping the take a look at power envelope in a very fully predictable, accurate, and versatile fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid theme efficiently combines check compression with LBIST, where each techniques will work synergistically to deliver top quality tests. Experimental results obtained for industrial styles illustrate the feasibility of the proposed take a look at schemes and are reported herein.

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Previous article: Design and synthesis of bandwidth efficient QPSK modulator for low power VLSI design - 2015 Design and synthesis of bandwidth efficient QPSK modulator for low power VLSI design - 2015 Next article: Power Optimization of Communication System Using Clock Gating Technique - 2015 Power Optimization of Communication System Using Clock Gating Technique - 2015
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