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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} - 2014
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} - 2014

PROJECT TITLE:

Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} - 2014

ABSTRACT:

Sign arithmetic is ineluctable in Digital Signal Processing algorithms. Due to the way signed integer is represented in Residue Number System (RNS), sign detection has been a difficult operation similar to the residue-to-binary conversion. In this project, a new sign detection method for the three moduli set RNS {2n, 2n-1, 2n +1} is proposed. It leverages the one complement and circular left shift properties of modulo 2n and 2n±1 arithmetic in the new modified Chinese Remainder Theorem for sign detection. Compared with the sign detector based on the most efficient reverse conversion algorithm, our proposed sign detector saves on average 24.5% of area and accelerates the computation by 45.6% for n = 5, 10, 15, 20.

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