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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults - 2015
Details
Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
Hits: 7

A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults - 2015

PROJECT TITLE:

A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults - 2015

ABSTRACT:

This project proposes a methodology of LFSR seed generation for deterministic and pseudo-random testing of static faults. The proposed technique directly generate seeds by using ATPG and avoids unsuccessful encoding of conventional two-pass generation strategies. The effectiveness of the proposed methodology is evaluated through experiments for several LFSRbased pseudo-random pattern generators. The quality of seeds generated by the proposed methodology is evaluated by stuck-at fault coverage when check patterns are expanded from seeds.

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