PROJECT TITLE :

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

ABSTRACT:

Fractional motion estimation (FME) considerably enhances video compression efficiency, but its high computational complexity also limits the $64000-time processing capability. During this transient, we tend to gift a VLSI implementation of FME design in High Potency Video Coding for ultrahigh definition video applications. We tend to initial propose a bilinear quarter pixel approximation, along with a pursuit pattern based on it to scale back the complexity of interpolation and fractional search method. Furthermore, a information reuse strategy is exploited to scale back the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we totally pipeline the computation and achieve high hardware utilization. This style has been implemented as a 65-nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for frames/s at 188 MHz, a minimum of 4.seven times faster than prior arts. The corresponding power dissipation is 198.half dozen mW, with a power efficiency of 0.a pair of nJ/pixel. Because of the optimization, our work achieves a lot of than 52% improvement on power potency, relative to previous works in H.264.