PROJECT TITLE :
1 TB/s one pJ/b six.4 $rm mm^2/rm TB/s$ inductive-coupling interface between 65-nm complementary metal–oxide–semiconductor (CMOS) logic and emulated one hundred-nm dynamic random access memory (DRAM) is developed. $rm BER<ten^-16$ operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to thirty two$times$, and therefore the energy consumption and therefore the layout area are reduced to 1/eight and 1/22, respectively.
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