Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board


A methodology for modeling the facility delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is predicated on inductance extraction from 1st principle formulation of a cavity fashioned by parallel metal planes. Circuit reduction is employed to practically realize the model for a production level, complicated, multilayer PCBs. The lumped component model is compatible with SPICE-type simulators. The resulting model has a comparatively easy circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model will be used for a wide range of geometry variations in an exceedingly power integrity analysis, together with complicated power/ground stack up, varied numbers of decoupling capacitors with arbitrary locations, various IC power pins and IC power/ground return via layouts, in addition to tons of ground come back vias.

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