A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming


An auto-zero and chopper operational amplifier with a four.5–60 V offer voltage vary is realized, employing a $hbox0.18~muhboxm$ CMOS process augmented by 5 V CMOS and sixty V DMOS transistors. It achieves a most offset voltage drift of zero.02$~mu hboxV/^circhboxC$ , a minimum CMRR of 145 dB, a noise PSD of $hbox6.8 nV/surdrm Hz$, and a 3.1 MHz unity gain bandwidth, while dissipating 840$~muhboxA$ of current. Up-modulated chopper ripple is suppressed by auto- zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the bulk of the glitch energy up to four.8 MHz, whereas leaving little energy at 80zero kHz. So, the necessities on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth will be obtained. Maximum input bias current due to charge injection mismatch is reduced from one.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry