Role of Device Dimensions and Layout on the Analog Performance of Gate-First HKMG nMOS Transistors


This paper discusses well the results of device dimensions and layout/style rules on the analog performance of gate-initial high-K gate dielectrics and metal gate (HKMG) nMOS transistors. It is observed through detailed measurements that the transconductance of HKMG nMOS transistors will increase with the reduction in the channel width. The 80-nm wide HKMG nMOS transistors show one.three× improvement in the intrinsic gain and ~27percent improvement in the transconductance generation potency compared with a one thousand-nm wide transistor. The similar behavior is observed for all gate lengths. The physical mechanisms accountable for this behavior are identified and explained. It's finally shown that the analog performance of the HKMG nMOS transistors might be further improved by dividing a single active finger into multiple active fingers, by increasing active-to-active spacing, by increasing the gate pitch, and by eliminating the active dummies.

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