Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

PROJECT TITLE :

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

ABSTRACT:

Previous high-performance delay-locked loops (DLLs) were designed during a full-custom style flow that's labor-intensive. Most of these DLLs need tens to hundreds of clock cycles to realize synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in an exceedingly cell-based mostly design flow. The proposed ADDLL circuit can acquire the phase of a clock signal from 60-MHz frequency to one.a pair of-GHz frequency. In this paper, the digitally controlled delay line (DCDL) is resettable such that our constant acquisition-cycle DLL algorithm can apply. This paper realizes the DCDL using lattice delay units in a very linear manner, therefore the delay profile of our DCDL shows smart linearity. On the other hand, the proposed ADDLL algorithm can effectively eliminate the harmonic lock. The ADDLL chip is implemented using the Artisan-TSMC-zero.eighteen- $murm m$ CMOS cell library. The measured power consumption of the chip is sixteen.a pair of mW at one.two-GHz clock frequency and at 1.eight V provide voltage. The rms jitter is one.sixty three ps and the peak-to-peak jitter is 12.eight ps. Both are measured at 1.two-GHz clock frequency.

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