Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory


As adopting a terribly powerful error-correcting code gradually becomes a strategic demand for the endurance of these days flash memory, LDPC codes are recently proposed because of their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the acute low error rate demand of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between very good error correcting capability and low error floor becomes another system structure. During this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980–983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability within the waterfall region whereas keeps low error floor.

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