PROJECT TITLE :
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
Although multiplying delay-locked loops allow clock frequency multiplication with terribly low part noise and jitter, their application has been so way restricted to integer-N multiplication, and therefore the achieved reference-spur performance has been usually restricted by time offsets. This paper presents the first revealed multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the section detector offset. Each capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented during a normal 65 nm CMOS method, occupies a core space of 0.09 mm two, and generates a frequency ranging between 1.vi and one.nine GHz with a one hundred ninety Hz resolution from a 50 MHz quartz-based mostly reference oscillator. In fractional-N mode, the integrated RMS jitter, as well as random and deterministic components, is below one.4 ps at three mW power consumption, resulting in a jitter-power figure of benefit of -232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at two.four mW power and figure of merit of -243 dB. Because of the adoption of the automatic offset cancellation, the reference-spur level is reduced from -32 to -fifty five dBc.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here