PROJECT TITLE :

Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach

ABSTRACT:

A sub-threshold design could give a compelling approach to power critical applications. An exponential relationship exists, but, between the delay and the edge voltage, that produces this style-time timing closure very difficult, if not not possible, to attain. Several previous studies were focused on the technique of body biasing throughout post-silicon tuning for delay compensation. But they were mostly for super-threshold designs where spatially correlated $L _mathbf eff$ variation dominates. They can't be applied on to sub-threshold styles in which purely random threshold voltage variations dominate. These works additionally assumed multiple body biasing voltage domains and multiple body biasing voltage levels, which involve important design overhead. The matter of selective body biasing for post-silicon tuning of sub-threshold designs is examined in this paper. The likelihood of using solely one body bias voltage domain with one body bias voltage is explored. The problem was formulated 1st as a linearly constrained statistical optimization model. The adaptive filtering concept from the signal processing community was then adopted so that an efficient, nevertheless novel, answer could be developed. Using several sixty five nm industrial designs, experimental results suggest that, compared with a seemingly additional intuitive approach, the proposed approach can improve the pass rate by 57p.c on average with similar standby power and the identical range of body biasing gates. This approach will reduce the standby power, on average, by 84p.c, with a 20percent pass rate loss, more than the approach to bias all the gates.