PROJECT TITLE :
A Differential 2R Crosspoint RRAM Array With Zero Standby Current
Memory power consumption dominates mobile system energy budgets in scaled technologies. Fast nonvolatile memory devices (NVMs) offer an incredible opportunity to eliminate memory leakage current during standby mode. Resistive random access memory (RRAM) in a crosspoint structure is considered to be one of the foremost promising rising NVMs. But, the absence of access transistors puts important challenges on the write/scan operation. In this brief, we tend to propose a differential 2R crosspoint structure with array segmentation and sense-before-write techniques. A sixty four-KB RRAM device is constructed and simulated in an exceedingly twenty eight/thirty two-nm CMOS predictive technology model and a Verilog-A RRAM model. This style offers an opportunity to use RRAM as a cache for increasing energy potency in mobile computing.
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