PROJECT TITLE :

An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors

ABSTRACT:

Chip multiprocessors (CMPs) need a low-latency interconnect cloth network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). Whereas packet-switched mesh interconnects sacrifice performance of many-core processors because of NoC-induced delays, existing circuit-switched interconnects don't supply lower network delays as they cannot hide the time it takes to set up a circuit. To handle this drawback, this work introduces CIMA—a hybrid circuit-switched and packet-switched mesh-based mostly interconnection network that affords low LLC access delays at a tiny area price. CIMA uses virtual cut-through (VCT) switching for short request packets, and benefits from circuit switching for longer, delay sensitive response packets. While an invitation is being served by the LLC, CIMA tries to set up a circuit for the corresponding response packet. By the time the request packet is served and therefore the response gets prepared, a circuit has already been prepared, and therefore, the response packet experiences short delay within the network. A detailed analysis targeting a 64-core CMP running scale-out workloads reveals that CIMA improves system performance by twenty one % over the state-of-the-art hybrid circuit-packet-switched network.