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PROJECT TITLE :

Parallel very large-scale integration chip implementation of optimal fractional motion estimation

ABSTRACT:

Fractional motion estimation (ME) is commonly employed to improve motion compensation in video coding. However, the computational complexity is generally too high for real-time applications. This study proposes an efficient quarter-pixel estimation method implemented at both the algorithm and architecture levels. This approach to rapid estimation adopts a local full-search method to reduce the computational requirements while maintaining coding quality. We also developed a fast sub-pixel interpolation and parallel very large-scale integration (VLSI) architecture for quarter estimation to enhance processing speed. The overall VLSI architecture was developed for the estimation of fractional motion using a cell-based design. Three engines were implemented within a parallel structure: integer ME, sub-pixel interpolation and factional ME. The inclusion of pipeline scheduling enables the processing of one macro-block within 240 cycles. The gate count was ~316 k and the maximum frequency was ~160 MHz when implemented using Taiwan Semiconductor Manufacture Company 0.18 μm complementary metal oxide semiconductor process. The proposed chip achieved a throughput-rate of 662 k blocks per second.


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