PROJECT TITLE :

Pipelined Architecture for a Radix-2 Fast Walsh–Hadamard–Fourier Transform Algorithm

ABSTRACT:

This transient proposes an efficient radix-two single-path delay commutator (SDC) pipelined architecture to implement the quick Walsh–Hadamard–Fourier remodel (FWFT) algorithm. The proposed design includes SDC stages, that are implemented by merged 0.5-butterfly. The merged 0.5-butterfly is proposed to achieve one hundred% hardware utilization and minimum buffer usage by sharing common merged half-butterflies in the time-multiplexed approach. Compared with the traditional pipelined radix-two FFT+Walsh–Hadamard Remodel (WHT) styles, the proposed design reduces the quantity of buffers by 50% and of adders by twenty five%. The desired range of advanced multipliers is decreased to , which is roughly the minimum range. Moreover, the proposed design can be applied to FFT/WHT/sequence-ordered complicated Hadamard rework (SCHT).