PROJECT TITLE :

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating

ABSTRACT:

In ancient decoupling capacitor topologies, power gating will significantly degrade the system-wide power integrity of a three-D integrated circuit since the decoupling capacitance associated with the ability-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: one) comparatively low-resistance through silicon vias (TSVs) and a couple of) ability of TSVs to bypass plane-level power networks when delivering the power offer voltage. In the proposed topologies, decoupling capacitors placed within a plane can give charge to neighboring planes even when the plane is power gated, achieving up to 50% and eighty seven% reduction in, respectively, rms power provide and power gating (in-rush current) noise at the expense of a moderate increase in physical space and peak power consumption.