A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter

PROJECT TITLE :

A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter

ABSTRACT:

This paper presents a half dozen-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique within the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by sixty ninep.c. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in an exceedingly sixty five-nm CMOS method technology. The peak integral nonlinearity and differential nonlinearity are measured as zero.52 and zero.fifty one LSB, respectively. At two.five GS/s, a symbol-to-noise and distortion ratio (SNDR) of eighteen.half dozen/thirty one.nine dB and a spurious-free dynamic range (SFDR) of 23.seven/42.one dBc are measured before and after the calibration at the Nyquist input frequency with one Vpp-diff input signal, and the figure of merit is zero.twenty seven pJ/conversion-step. This chip consumes 22 mW at 1.a pair of-V offer and occupies zero.twenty seven-mm2 space.

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