PROJECT TITLE :
A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor
ABSTRACT:
A design of a 10-bit 27.8 kS/s zero.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt vary power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage style. To facilitate ultra-low voltage operation, a bulk-driven based totally dynamic comparator is proposed. A completely unique latched dynamic logic cell is introduced to eliminate call error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to alleviate non-linearity. A replacement double-boosted sample switch is employed to scale back leakage current and improve sampling linearity. The ADC was fabricated in sixty five nm complementary metal oxide semiconductor. Drawing twenty five.2 nW from one 350 mV offer, the ADC achieves 52.fourteen dB signal-to-noise distortion ratio and eight.four-bit effective number of bits ensuing in an exceedingly figure-of-benefit of two.67 fJ/conversion-step.
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