Feature detection for image analytics via FPGA acceleration


With the expansion of multimedia information generation and consumption, image-based mostly data analytics plays an increasingly vital role in huge information analytics systems. For image analytics, feature detection algorithms offer a foundation for a selection of image-based applications. These algorithms are typically computationally intensive and therefore are sensible candidates for acceleration with field programmable gate arrays (FPGAs). In this paper, we have a tendency to investigate a Harris-Laplace variant of scale-invariant feature detection, a widely used image analytics algorithm, to demonstrate the aptitude of acceleration. Primarily based on stream computing, we tend to construct a totally pipelined implementation which will method one pixel per FPGA clock cycle. Our implementation considerably outperforms the present revealed work. The proposed implementation adopts a single-precision floating-purpose illustration and can detect the features of 640 480-pixel images at 540 frames per second. This throughput is sufficient for multistream real-time video interpretation.

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