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26 . Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction - 2017 Abstract
27 . High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder - 2017 Abstract
28 . Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression - 2017 Abstract
29 . Design and Analysis of Multiplier Using Approximate 15-4 Compressor - 2017 Abstract
30 . Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication - 2017 Abstract
31 . Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic - 2017 Abstract
32 . Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems - 2017 Abstract
33 . DSP48E Efficient Floating Point Multiplier Architectures on FPGA - 2017 Abstract
34 . Fast Energy Efficient Radix-16 Sequential Multiplier - 2017 Abstract
35 . A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n− 1, 2n+ 1, 22n+ 1, 22n+p} - 2017 Abstract
36 . Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017 Abstract
37 . Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx - 2017 Abstract
38 . Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing - 2017 Abstract
39 . Design of Power and Area Efficient Approximate Multipliersc - 2017 Abstract
40 . Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers - 2017 Abstract
41 . A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers - 2017 Abstract
42 . A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2017 Abstract
43 . High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017 Abstract

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