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1 |
A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS - 2018 |
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2 |
A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators - 2018 |
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3 |
A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads - 2018 |
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4 |
A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm - 2018 |
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5 |
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic - 2018 |
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6 |
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications - 2018 |
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7 |
Effect of Switched-Capacitor CMFB on the Gain of Fully Differential OpAmp for Design of Integrators - 2018 |
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8 |
Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique - 2018 |
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9 |
Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique - 2018 |
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10 |
Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder - 2018 |
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11 |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates - 2018 |
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12 |
Passive Noise Shaping in SAR ADC With Improved Efficiency - 2018 |
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13 |
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation - 2018 |
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