PROJECT TITLE :

Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

ABSTRACT:

Embedded field programmable gate arrays (eFPGA) can give fashionable systems-on-a-chip (SoCs) with the flexibleness required to face the expansion of nonrecurring engineering and producing costs. On the other hand, SoC designers sometimes understand eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and space tradeoff since they are typically accessible as custom-designed hard macros. In this situation, technology scaling is permitting designers to cut back the impact of the eFPGA space gap, whereas effective exploitation of all the technology choices (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application desires. In this paper, we have a tendency to propose an look-up table-based soft-core eFPGA that includes a synthesizable and parametric architecture. A key purpose of our proposal is that we have a tendency to have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a considerably wide style-space accessible on very totally different technologies (we have a tendency to experimented STMicroelectronics CMOS sixty five nm and BCD9s zero.eleven ). Application-driven evaluation showed how for a fastened eFPGA size (i.e., number of logic blocks) totally different configurations of the MSSN allow designers to hurry up performance by twenty/sixty%, with to maximise the computational density for a given space budget.