PROJECT TITLE :

Fast and Scalable Computation of the Forward and Inverse Discrete Periodic Radon Transform

ABSTRACT:

The discrete periodic radon rework (DPRT) has extensively been utilized in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can additionally be used to compute quick convolutions that avoids the use of floating-purpose arithmetic associated with the use of the fast Fourier rework. Unfortunately, the use of the DPRT has been limited by the necessity to compute a giant number of additives and the need for a massive variety of memory accesses. This paper introduces a fast and scalable approach for computing the forward and inverse DPRT that is based mostly on the utilization of: 1) a parallel array of mounted-point adder trees; a pair of) circular shift registers to get rid of the need for accessing external memory components when selecting the input data for the adder trees; three) a picture block-based approach to DPRT computation that may fit the proposed architecture to accessible resources; and 4) quick transpositions that are computed in one or some clock cycles that don't depend on the size of the input image. Therefore, for an $Ntimes N$ image ( $N$ prime), the proposed approach can compute up to $N^2$ additions per clock cycle. Compared with the previous approaches, the scalable approach provides the fastest known implementations for different amounts of computational resources. For instance, for a $251times 251$ image, for roughly twenty five% fewer flip-flops than required for a systolic implementation, we tend to have that the scalable DPRT is computed 36 times faster. For the fastest case, we have a tendency to introduce optimized architectures that may compute the DPRT and its inverse in simply $2N+left lceil log _2Nright rceil +1$ - /tex-math> and $2N+3left lceil log _2Nright rceil +B+two$ cycles, respectively, where $B$ is the number of bits used to represent every input pixel. On the opposite hand, the scalable DPRT approach requires additional 1-b additions than for the systolic implementation and provides a tradeoff between speed and additional one-b additions. All of the proposed DPRT architectures were implemented in VHSIC Hardware Description Language (VHDL) and validated using an Field-Programmable Gate Array (FPGA) implementation.