PROJECT TITLE :

High-speed time interleaved ADCs

ABSTRACT:

Software-defined multi-gigahertz receivers require high-speed ADCs at the frontend. Time interleaving has emerged as the most common technique of achieving ultra-quick quantization at moderately high resolution. But, this multi-path solution introduces systematic errors because of mismatches in signal methods, whereas in non-interleaved versions these were mixed to DC, where they appeared as a harmless offset. Mitigating all potential time-interleaved errors comes at a serious value in complexity, risk, and power. Knowing that errors are most vital and which can be neglected in any given application is important for choosing an acceptable architecture and calibration scheme. Pointers for reducing errors result in potentially completely different design selections. When the goal is to use the fewest slices, an inerleaved pipelined ADC results, whereas when the overriding objective is to use the simplest slice potential, a massive array of SAR slices is typically adopted. Both approaches have advantage. This article addresses when and where to use every approach by discussing specification necessities and showing that completely different types of error sources should not be merged into one single metric like ENOB, but ought to be treated separately to determine their impact on overall system performance. An example of an eight-approach interleaved pipelined ADC is presented, which illustrates these principles in the context of a real circuit.