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  4. Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors - 2016
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Category: MTech VLSI Projects
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MTech Projects
01.Jun
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Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors - 2016

PROJECT TITLE :

Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors - 2016

ABSTRACT:

In many digital signal processing applications, some components of a word stored in the embedded static random access reminiscences (SRAMs) are more important than other components of the word. Due to the differences in importance, memory failures that occur in more important bit locations typically provide rise to relatively larger system performance degradation than those in less necessary locations. This brief presents an occasional-complexity unequal-error-protection error correcting code (UEEP-ECC) approach for the embedded reminiscences in digital signal processor. In the proposed UEEP-ECC, repetition code is combined with the Bose-Chaudhuri-Hocquenghem code to selectively provide stronger error correction capabilities on a lot of necessary knowledge portions without a massive hardware overhead. An efficient UEEP-ECC generation algorithm that may notice the UEEP-ECC code with a minimum power of memory core and ECC logics is additionally presented. The experimental results show that the UEEP-ECC scheme achieves considerable power savings and data quality enhancements in each of the H.264 and fast Fourier rework applications.

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  • ROOT
  • BCH Codes
  • SRAM Chips
  • Error Correction Code (ECC)
  • Static Random Access Memory (SRAM)
  • Unequal-Error-Protection (UEEP)
Previous article: Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 Next article: Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016 Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016
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