PROJECT TITLE :

Ultralow-Energy Variation-Aware Design: Adder Architecture Study - 2016

ABSTRACT:

Power consumption of digital systems is an important issue in nanoscale technologies and growth of method variation makes the matter a lot of difficult. During this temporary, we have a tendency to have analyzed the latency, energy consumption, and effects of process variation on completely different structures with respect to the planning structure and logic depth to propose architectures with higher throughput, lower energy consumption, and smaller performance loss caused by method variation in application-specific integrated circuit style. We tend to have exploited adders as different implementations of a processing unit, and propose architectural pointers for finer technologies in subthreshold which are applicable to any alternative architecture. The results show that smaller computing building blocks have higher energy efficiency and less performance degradation because of variation effects. In contrast, their computation throughput can be mid or less unless correct solutions, such as pipelined or parallel structures, are used. Therefore, our proposed solution to boost the throughput loss whereas reducing sensitivity to process variations is using simpler components in deep pipelined styles or massively parallel structures.