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  4. Truncated ternary multipliers - 2015
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Category: MTech VLSI Projects
By MTech Projects
MTech Projects
01.Jun
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Truncated ternary multipliers - 2015

PROJECT TITLE:

Truncated ternary multipliers - 2015

ABSTRACT:

Several times in the history of computing, balanced ternary range illustration and arithmetic, based mostly on the symmetric radix-3 digit collection -1, 0, +1, have been studied. Representative symmetry, favorable error features and rounding by truncation are among the established advantages of balanced ternary arithmetic. We have a tendency to display an additional gain in this study: that of lower-error truncated multiplication with the same relative price decrease as in truncated binary multipliers.

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Previous article: Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015 Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs - 2015 Next article: An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm - 2015 An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm - 2015
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