PROJECT TITLE :

PNS-FCR: Flexible Charge RecyclingDynamic Circuit Technique forLow-Power Microprocessors - 2016

ABSTRACT:

Due to the superior speed and area characteristics, dynamic circuits are widely applied in information ways and other time vital parts in trendy microprocessors. The high switching activity of dynamic circuits, however, consumes vital power. During this paper, a p-sort/n-sort dynamic circuit choice (PNS) algorithm and a flexible charge recycling (FCR) design methodology are proposed to achieve high power efficiency in information ways. The effects of technology scaling, knowledge path width, design complexity, clock skew, and environmental conditions are mentioned. Simulation results show that the ability consumption of an arithmetic and logic unit (ALU) with the proposed PNS-FCR can be reduced by up to 60% as compared with a standard ALU. An eight-bit ALU take a look at circuit has also been manufactured primarily based on a 0.thirty five-µm Global Foundries technology, demonstrating the power and area potency of the proposed methodology.