The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation

Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (2010)

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits - 2015

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC - 2015

Towards Low Power Approximate DCT Architecture for HEVC Standard - 2017

Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder - 2018

Implementation of a visible Watermarking in a secure still digital Camera using VLSI design

Multiplexer based High Throughput S-box for AES Application - 2015

Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO - 2015

All Optical Reversible Multiplexer Design using Mach-Zehnder interferometer