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  4. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016
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Category: MTech VLSI Projects
By MTech Projects
MTech Projects
01.Jun
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Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016

PROJECT TITLE:

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016

ABSTRACT:

Soft errors cause a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for several applications. Communications and signal processing systems aren't any exceptions to the present trend. For some applications, an interesting possibility is to use algorithmic-primarily based fault tolerance (ABFT) techniques that try to use the algorithmic properties to detect and proper errors. Signal processing and communication applications are well fitted to ABFT. One example is quick Fourier transforms (FFTs) that are a key building block in many systems. Many protection schemes are proposed to detect and proper errors in FFTs. Among those, most likely the use of the Parseval or sum of squares check is the most widely known. In modern communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a way that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this temporary, this technique is 1st applied to guard FFTs. Then, 2 improved protection schemes that mix the employment of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can more reduce the implementation value of protection.

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Previous article: Fault Tolerant Parallel Filters Based on Error Correction Codes - 2015 Fault Tolerant Parallel Filters Based on Error Correction Codes - 2015 Next article: A novel VHDL implementation of UART with single error correction and double error detection capability - 2015 A novel VHDL implementation of UART with single error correction and double error detection capability - 2015
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