PROJECT TITLE :

Area-Aware Cache Update Trackers for Post silicon Validation - 2016

ABSTRACT:

The internal state of the complex fashionable processors usually desires to be dumped out frequently during postsilicon validation. Since the caches hold most of the state, the degree of knowledge dumped and the transfer time are dominated by the big caches gift in the design. The restricted bandwidth to transfer data gift in these large caches off-chip leads to stalling the processor for long durations when dumping the cache contents off-chip. To alleviate this, we tend to propose to transfer solely those cache lines that were updated since the previous dump. Since maintaining a bit-vector with a separate bit to trace the standing of individual cache lines is pricey, we propose two ways: 1) where a touch tracks multiple cache lines and 2) an Interval Table that stores only the beginning and ending addresses of continuous runs of updated cache lines. Each methods need considerably lesser space compared with a bit-vector, and allow the designer to choose the quantity of house to allocate for this design-for-debug feature. The impact of reducing space for storing is that some nonupdated cache lines are dumped too. We have a tendency to attempt to reduce such overheads. We have a tendency to propose a scheme to share such cache update tracking hardware (or Update Trackers) across multiple caches in case of physically distributed caches thus that they're replicated fewer times, thereby limiting the world overhead. We tend to show that the proposed Update Trackers occupy but 1p.c of cache area for each the shared and distributed caches.