PROJECT TITLE:

An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge - 2014

ABSTRACT:

As microprocessor performance has relentlessly improved lately, it's become increasingly important to produce a high-bandwidth, low-latency memory subsystem to realize the total performance potential of these processors. In the past years, improvements in memory latency and bandwidth have not kept pace with reductions in instruction execution time. Caches are used extensively to patch over this mismatch, however some applications don't use caches effectively. The result is that the memory access time has been a bottleneck that limits the system performance. A Memory Controller is intended to cater to this problem. The Memory Controller may be a digital circuit that manages the flow of information going to and from the most memory. It can be a separate chip or can be integrated into the system chipset. This project revolves around building an Advanced Microcontroller Bus Architecture (AMBA) compliant Memory Controller as an Advanced High-performance Bus (AHB) slave. The whole style is captured using Verilog HDL, simulated with ModelSim and configured to a FPGA target device belonging to the Virtex4 family using Xilinx