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Category: MTech DSP Projects
By MTech Projects
MTech Projects
28.Nov
Hits: 61

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems - 2018

PROJECT TITLE :

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems - 2018

ABSTRACT:

As a branch of sphere decoding, the K-best method has played an vital role in detection in large-scale multiple-input-multiple-output (MIMO) systems. However, because the numbers of users and antennas grow, the preprocessing complexity increases considerably, that is one in every of the key problems with the K-best method. To handle this problem, this Project proposes a preprocessing algorithm combining Cholesky sorted QR decomposition and partial iterative lattice reduction (CHOSLAR) for K-best detection in a very sixty four-quadrature amplitude modulation (QAM) 16 × sixteen MIMO system. Initial, Cholesky decomposition is conducted to perform sorted QR decomposition. Compared with typical sorted QR decomposition, this technique reduces the amount of multiplications by 25.onepercent and increases parallelism. Then, a constant-throughput partial iterative lattice reduction method is adopted to realize near-optimal detection accuracy. This method more will increase parallelism, reduces the number of matrix swaps by 45.fivep.c, and reduces the amount of multiplications by 67.threep.c. Finally, a sorting-reduced K -best strategy is used for vector estimation, thereby, reducing the quantity of comparators by 84.7%. This technique suffers an accuracy loss of solely approximately 1.forty four dB compared with most probability detection. Primarily based on CHOSLAR, this Project proposes a absolutely pipelined terribly-massive-scale-integration design. A series of various systolic arrays and parallel processing units achieves an optimal tradeoff among throughput, space consumption, and power consumption. This architectural layout is obtained via TSMC 65-nm 1P9M CMOS technology, and throughput metrics of one.forty Gbps/W (throughput/power) and 0.sixty two Mbps/kG (throughput/space) are achieved, demonstrating that the proposed system is much more efficient than state-of-the-art designs.

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