PROJECT TITLE :

Transistor–resistor-stacked voltage-mode PAM-4 symbol generator with improved linearity

ABSTRACT:

To address the restricted linearity range of current-mode logic circuits used for four-level pulse amplitude modulation (PAM-4) image generation, a voltage-mode, inverter-like circuit that includes a stacked transistor-resistor structure is proposed. Simulation results have shown that the linearity of the proposed PAM-four circuit has been improved by 43.one%, with a modest increase of circuit area. Additionally, 20percent resistance mismatch in the proposed PAM-4 symbol generator ends up in linearity degradation of <;nine%.