PROJECT TITLE :

Bulk-Accumulation Oxide Thin-Film Transistor Circuits With Zero Gate-to-Drain Overlap Capacitance for High Speed

ABSTRACT:

The overlap between gate and supply/drain electrodes gives rise to parasitic capacitance ( /), that causes RC signal delay in skinny-film transistor (TFT) circuits. Here, we have a tendency to show that in amorphous-indium–gallium–zinc-oxide TFTs, offsets as giant as , result in only slight reductions in drain-current, such that (compared with single-gate TFTs with 2.5- gate-to-supply/drain overlaps) an overall 3 times increase in switching speed can be achieved in twin-gate TFTs with offset high-gates shorted to offset bottom-gates. The high switching speed ( ns/stage delay), which is a combined impact of the majority-accumulation achieved by shorting the two gates and nil , leads to high-speed amorphous oxide TFT-based mostly circuits.