PROJECT TITLE :

Novel Multi-Level Cell TFT Memory With an In–Ga–Zn-O Charge Storage Layer and Channel

ABSTRACT:

For the first time, multi-level cell memory applications using amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor nonvolatile memory devices with an IGZO charge storage layer were evaluated. After applying a positive gate voltage pulse (for instance, 12 V for 10 milliseconds), the original state (OS) of the device can be switched to the programmed state (PS), and after applying a negative gate voltage pulse, the erased state (ES) of the device can be applied. The pristine device was defined as the original state (OS) (for example, -15 V for 10 ms). Under conditions of a positive gate bias, the writing mechanism was thought to involve Fowler-Nordheim tunneling of electrons from the channel to the charge storage layer. Under conditions of a negative gate bias, the writing mechanism was thought to involve inverse tunneling. Electrically programmable and erasable capabilities were significantly improved by the devices. After 100 programming and erasing cycles, the memory window between OS and PS remained at 2.4 V, and the memory window between OS and ES remained at 2.66 V. Both memory windows were maintained. For a retention time of 10 5 s, the memory windows relative to OS are equal to 1.91 V for PS and 1.30 V for ES, respectively.