PROJECT TITLE :

High gain two-stage amplifier with positive capacitive feedback compensation

ABSTRACT:

A completely unique topology for a high gain 2-stage amplifier is proposed. The proposed circuit is meant in a very way that the non-dominant pole is at output of the primary stage. A positive capacitive feedback around the second stage introduces a left half-plane zero, that cancels the part shift introduced by the non-dominant pole, significantly. The dominant pole is at the output node, that suggests that that increasing the load capacitance has minimal effect on stability. Moreover, a straightforward and effective method is proposed to reinforce slew rate. Simulation shows that slew rate is improved by a issue of 2.44 using the proposed technique. The proposed amplifier is intended in an exceedingly 0.18 μm complementary metal-oxide-semiconductor method. It consumes 0.eighty six mW power from a 1.8 V power provide and occupies 3038.five μm2 of chip space. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.nine MHz when driving a five pF capacitive load. Additionally low frequency common-mode rejection ratio and positive power offer rejection ratio are 127 and eighty three.a pair of dB, respectively. They are twenty four.8 and twenty four.2 dB at GBW frequency, that are comparatively high and are alternative vital properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in method corners and also the presence of a mismatch.