PROJECT TITLE :

Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL

ABSTRACT:

Several state-of-the-art monitoring and management systems, like dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, need direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals need high linearity and low-voltage coefficient capacitors. A designed-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-to-digital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in every capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally throughout traditional ADC operation. The algorithm is implemented on a fourteen-bit HV input vary SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6-μm HV-compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, that is an improvement of twelve.03 dB when self-calibration at 400-kS/s sampling rate, consuming ninety mW from a ±fifteen V offer. The calibration circuitry occupies twenty eightp.c of the capacitor DAC and consumes <;fifteen mW during operation. Measurement results show that this algorithm reduces integral nonlinearity from as high as seven LSBs right down to one LSB, and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from ten LSBs all the way down to 1 LSB. The ADC occupies an energetic area of 9.76 mm2.