PROJECT TITLE :

A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-standard and Multimode Turbo Decoding - 2016

ABSTRACT:

The multiplication of wireless Communication standards is introducing the requirement of versatile and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders are recently developed in order to support the increasing flexibility and throughput necessities of rising applications. However, these solutions do not sufficiently address reconfiguration performance issues, that will be a limiting issue in the long run. This temporary presents the planning of a reconfigurable multiprocessor architecture for turbo decoding achieving terribly quick reconfiguration without compromising the decoding performances.


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Decoding Turbo Codes Application Specific Integrated Circuits Wireless Communication Application Specific Instruction-Set Processor (Asip) Dynamic Configuration Turbo Codes (TCS)
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