Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication - 2017 PROJECT TITLE :Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication - 2017ABSTRACT:Decimal X × Y multiplication may be a complicated operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix-ten X multiples. Some works need solely [0, five] × X via recoding digits of Y to one-hot illustration of signed digits in [-five,5]. This reduces the selection logic at the price of 1 extra IPP. 2's complement signed-digit (TCSD) encoding is typically used to represent IPPs, where dynamic negation (via one xor per little bit of X multiples) is needed for the recoded digits of Y in [-five, -1]. In this paper, despite generation of seventeen IPPs, for sixteen-digit operands, we manage to begin the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save seventy fivepercent of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the primary-level PPR, we devise an economical adder, with 2 SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:one reduction results in 2 TCSD accumulated partial product, that collectively bear a special early initiated conversion scheme to urge at the final binary-coded decimal product. As such, a VLSI implementation of sixteen × sixteen-digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects Design and Analysis of Multiplier Using Approximate 15-4 Compressor - 2017 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic - 2017
