Efficient FPGA implementation of convolution

ABSTRACT:

Many image processing operations such as scaling and rotation need re-sampling or convolution filtering for every pixel in the image. Convolutions on digital pictures are necessary since they represent operations that are more general than the operations that may be performed on analog pictures. Convolution has many applications that have great significance in discrete signal processing. It's typically difficult to deal with analog signals. Hence signals are converted to digital state. Filtering of signals is terribly necessary in order to see which one to accept and that one to reject, and all of that is done by convolution.

This paper presents an on the spot methodology of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this analysis is to prove the feasibility of an FPGA that performs a convolution on an acquired image in real time. The proposed implementation uses a changed hierarchical design approach, which efficiently and accurately quickens computation; reduces power, hardware resources, and area considerably. The efficiency of the proposed convolution circuit is tested by embedding it during a prime level FPGA. In addition, the presented circuit uses less power consumption and delay from input to output. It additionally provides the required modularity, expandability, and regularity to form different convolutions for any variety of bits.

APPLICATION:

  • Image Compression Applications

ADVANTAGES:

  • Power reduction
  • Reduction of Hardware complexity

LANGUAGE USED:

  • Verilog HDL
  • TOOLS REQUIRED:
  • MODELSIM – Simulation
  • XILINX-ISE – Synthesis


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