Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

PROJECT TITLE :

Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

ABSTRACT:

High throughput whereas maintaining low resource could be a key issue for elliptic curve cryptography (ECC) hardware implementations in several applications. In this transient, an ECC processor architecture over Galois fields is presented, that achieves the most effective reported throughput/area performance on field-programmable gate array (FPGA) up to now. A unique segmented pipelining digit serial multiplier is developed to hurry up ECC purpose multiplication. To achieve low latency, a new combined algorithm is developed for purpose addition and point doubling with careful scheduling. A compact and versatile distributed-RAM-based memory unit style is developed to extend speed while keeping area low. More optimizations were made via timing constraints and logic level modifications at the implementation level. The proposed design is implemented on Virtex4 (V4), Virtex5 (V5), and Virtex7 (V7) FPGA technologies and, respectively, achieved throughout/slice figures of 19.sixty five, sixty five.30, and sixty four.48 .

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